Contact LogicVisionSite Map
LogicVision SolutionsLogicVision ProductsCompanyLogicVision SupportInvestorsLogicVision News and Events

Support > Training > Details

Training Details

Objectives

At the end of the class, the student should be able to:

  • Understand the value of LogicVision's Embedded Test (ET) solution
  • Perform DFT design rule checking on a chip design for embedded memory test
  • Generate, insert, and verify Embedded Memory Test (EMT) IP in a design
  • Perform DFT design rule checking on a chip design for embedded digital logic test
  • Generate, insert, and verify Embedded Logic Test (ELT) IP in a hierarchical logic cores
  • Generate, insert, and verify scan chains in hierarchical logic cores
  • Analyze fault coverage and insert test points to increase fault coverage
  • Perform DFT design rule checking on a chip design for TAP and boundary scan test
  • Generate, insert, and verify the TAP and boundary-scan logic at the chip level

Student Profile

This class is for logic design engineers who understand IC DFT concepts (i.e., Scan-ATPG-ATE) and tools and need to understand DFT Embedded Test IP tools and DFT Embedded Test IP methodologies. This course is also suitable for test engineers who want to understand how Embedded Test will impact their test flow.

Prerequisites

  • 2 years experience in ASIC design using RTL
  • 2 years experience using DFT tools for scan insertion and ATPG
  • Basic understanding of DFT flows and DFT methodology
  • Experience with HDL-based logic synthesis
  • Experience with UNIX directories and editing text files (for lab exercises)

Training Overview

Day 1: 9AM – 5PM: Embedded Memory Test, TAP, and Boundary Scan Flow

  • Introduction to LogicVision
  • Basics of Embedded Memory Test (EMT), TAP, and Boundary Scan
  • EMT, TAP, and Boundary Scan Flow and Setup
  • RTL/GATE Level DFT Insertion Steps w.r.t EMT, TAP, and Boundary Scan
    • Embedded Test Rule Checking using ETChecker
    • Embedded Test Planning using ETPlanner
    • Embedded TestInsertion using ETAssemble
    • Embedded Test Sign-off
  • Post-Silicon Debug Demonstration using Embedded Test Access (ETA)
  • Tutorial: User Driven Lab: Chip-level EMT, TAP, and Bscan Test Insertion using Flat Flow

Day 2: 9AM – 5PM: Embedded Logic Test Flow

  • Scan and Logic BIST Concepts
  • New Burst-Mode LogicBist
  • Hierarchical Test Approach
  • Embedded Logic Test (ELT) Flow and Setup
  • RTL/GATE Level DFT Insertion Steps w.r.t ELT
    • Embedded Test Rule Checking using ETChecker
    • Embedded Test Planning using ETPlanner
    • Embedded Test Insertion using ETAssemble
    • Scan Stitching using ETScan
    • Embedded Test Sign-off
  • Tutorials: User Driven Lab: Chip-level ELT Test Insertion using Hierarchical Flow

Labs

The labs are provided at each day of class. Each lab consists of hands-on exercises designed to reinforce the topics covered in the lecture.

Class Information

  1. See the LogicVision training schedules.
  2. Upon request, training is available on-site at the customer's location. Please contact your LogicVision sales representative to request an on-site training class.