Test for Low DPM
As new technologies continue to increase transistor densities and operating speeds, new test approaches are needed to achieve very low DPM levels. With smaller geometries there are un-modeled (un-anticipated) failure mechanisms that are often missed with the traditional stuck-at fault models used by ATPG based test methodologies. In particular, new classes of defects which affect the performance of the device are becoming common. LogicVision’s logic BIST solution, ETLogic™, is uniquely capable of addressing today’s rapidly growing quality and time-to-market challenges. The solution’s Burst-Mode architecture provides highly accurate at-speed test timing as well as very high transition fault coverage. This coupled with high N-detect coverage due to large random pattern counts results in the lowest possible DPM levels. The elimination of any test pattern debug coupled with fully automated diagnostic tools also results in significant savings in silicon bring-up time.
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Expect more from your test solution. Think LogicVision. Click here to learn more about ETLogic. |
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