ETSerdes - Embedded SerDes Test
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Paper: Why Use ETSerdes™ to Test High-Speed Serial I/Os?
Serializer/deserializer (SerDes) I/Os have become the dominant way to increase data handling capability while reducing power and pin-count for most new digital ICs. There are many popular SerDes standards, including PCI-Express, XAUI, SONET, Fibre-Channel, SATA, and USB. Testing multi-gigahertz SerDes performance with automatic test equipment (ATE) requires either adding jitter measurement equipment to low cost ATE and accepting long test times or buying state-of-the-art new ATE for possibly millions of dollars.
Writing test programs for multiple SerDes protocols, simulating without the ATE interface included, and correlating ATE measurements to bench-top measurements can require many months. At data rates below 4 Gb/s, many companies choose to simply forego jitter measurement in production and rely on well-characterized SerDes macros in a stable silicon process. They may also simply test that a large number of bits, say 100M, can be transmitted error free. At 5 Gb/s and higher, as wire characteristics dominate, characterization alone is proving insufficient – at least some jitter and equalization testing is necessary.
LogicVision's ETSerdes built-in-self-test (BIST) solution provides complete, parametric, embedded test for multi-Gb/s SerDes. It can measure waveshape, many types of jitter, and various jitter tolerance parameters, all in less than 200 ms, including test set-up and on-chip comparison to test limits via an IEEE 1149.1 TAP interface. ETSerdes uses purely digital, unlimited time-resolution analysis (ULTRA) patented technology connected to only the SerDes parallel ports, and has been proven on customer silicon operating faster than 10 Gb/s. One 10k-gate ULTRA module can test any number of SerDes lanes, and a TAP (or IEEE 1500 WTAP) can interface to any number of ULTRA modules.
ULTRA technology uses undersampling to achieve virtually unlimited, silicon-proven time resolution – from 1 second to 100 femtoseconds – using a purely digital analysis logic block synthesized from RTL in a standard digital design flow. Undersampling, when high frequencies are sampled by lower frequencies, is used by most test equipment and is often described as equivalent time sampling, mixing down, or aliasing.
LogicVision's ETSerdes delivers the following benefits:
- Shortened time-to-market: Characterize with PC plus GPIB-controlled
benchtop equipment or μWire-controlled clock conditioner PLL
- Lower cost test: Picosecond accuracy for any SerDes, on any ATE
- Improved yield: Unique diagnostic tests at production speeds