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ETPLL - BIST Solution for Testing PLLs

Datasheet

ETPLL BIST Solution

ETPLL provides complete, parametric, embedded test for PLLs, DLLs, and clock signals. It can measure jitter, phase delay, duty cycle, lock time, and lock range, all in less than 100 ms, including test set-up and on-chip comparison to test limits via the IEEE 1149.1 TAP interface. ETPLL uses the same, purely digital, unlimited time-resolution analysis (ULTRA) patented technology as ETSerdes, proven in silicon for 1~10 Gb/s. One 10k-gate ULTRA module can test any number of PLLs, and a TAP controller (or IEEE 1500 WTAP) can interface to any number of ULTRA modules. ETPLL delivers the following benefits:

  • Shortened time-to-market: Characterize with PC plus GPIB-controlled benchtop equipment or μWire-controlled clock conditioner PLL
  • Improved yield: Diagnostic tests at production speeds
  • Lower cost test: Picosecond accuracy for any PLL, on any ATE

While LogicVision delivered a first-generation BIST solution for PLLs in 1997, ETPLL is an entirely new approach to PLL testing, removing limitations of previous approaches including ATE-based testing.  ETPLL uses delay-line-free ULTRA technology to improve measurement capabilities by more than 10X. The purely digital implementation also facilitates a simpler, more flexible design flow.

ULTRA technology uses under-sampling to achieve virtually unlimited, silicon-proven time resolution—from 1 second to 100 femtoseconds—using a purely digital analysis logic block synthesized from RTL in a standard digital design flow. The stimulus for the PLL-under-test is its normal reference clock (or data) with any amount of jitter. In addition, control of the PLL’s internal dividers, using normal functional access, can be exploited to cause the PLL to lose lock or strive for output frequencies at the limits of its lock range.

Capturing the response is accomplished using simple latches or D-type flip-flops, which may be single-ended or, when measuring sub-picosecond jitter, differential. Sampling is accomplished with a second reference clock having high frequency-resolution and low jitter. All tests can be applied to delay-lock loops (DLLs) and clock signals or any other periodic signals.